1. Technical Field
The present invention relates to an electrostatic protection circuit that protects an internal circuit of a semiconductor integrated circuit apparatus from ESD (Electro-Static Discharge). Furthermore, the invention relates to a semiconductor integrated circuit apparatus having such an electrostatic protection circuit built therein.
2. Related Art
Semiconductor integrated circuit apparatuses are provided with an electrostatic protection circuit in order to prevent damage to an internal circuit due to static electricity that has accumulated in a human body or a transport machine being applied to the internal circuit. For example, the electrostatic protection circuit is connected between a first terminal that is supplied with a power supply potential on the high potential side and a second terminal that is supplied with a power supply potential on the low potential side. If a positive charge is applied to the first terminal due to an electrostatic discharge, the positive charge is released to the second terminal via the electrostatic protection circuit, thus preventing excessive voltage from being applied to the internal circuit and making it possible to prevent damage to the internal circuit.
As related technology, FIG. 9 of JP-A-2009-182119 shows a known electrostatic discharge protection circuit that is connected between a first power line and a second power line. This electrostatic discharge protection circuit includes a time constant circuit 101 constituted by a resistor and a capacitor that are connected in series between the first power line and the second power line, a discharge circuit constituted by an N-channel transistor 102 that is connected between the first power line and the second power line, and three stages of inverters 103 to 105 whose input sides are connected to connection nodes between the resistor and the capacitor, and whose output sides are connected to the gate of the transistor 102.
In this electrostatic discharge protection circuit, in the case where a positive charge is applied to the first power line, if the rise time of the potential of the first power line is shorter than the time that corresponds to the time constant of the time constant circuit 101, the potential at the connection nodes between the resistor and the capacitor falls to the low level. The potential at the connection nodes between the resistor and the capacitor is maintained at the low level in the period that corresponds to the time constant of the time constant circuit 101. In this period, the gate of the transistor 102 rises to the high level, and the transistor 102 enters the on state. Accordingly, the positive charge applied to the first power line is released to the second power line, and the internal circuit is protected.
In this way, in the electrostatic discharge protection circuit shown in FIG. 9 of JP-A-2009-182119, the start condition and the end condition of the discharge operation are determined by the time constant of the one time constant circuit 101. Accordingly, if the time constant is set such that the discharge operation is started only in the case where a rise in the applied voltage is steep, there is a risk of the duration of the discharge operation being insufficient. On the other hand, if the time constant is set so as to ensure a sufficient duration for the discharge operation, there is a risk of the electrostatic discharge protection circuit mistakenly operating when the power supply voltage rises at the time of power activation.
Also, in the electrostatic discharge protection circuit shown in FIG. 9 of JP-A-2009-182119, current starts to flow through the transistor 102 from an operation region in which the voltage between the first power line and the second power line is lower than the minimum operation voltage of the internal circuit. Accordingly, if the electrostatic discharge protection circuit operates when the power supply voltage rises at the time of power activation, there is a risk of the internal circuit mis-operating. This electrostatic discharge protection circuit needs to be used with a limit placed on the rise time of the power supply voltage at the time of power activation.
Furthermore, JP-A-2014-132717 discloses an electrostatic discharge protection circuit that can cause all of the charge produced by electrostatic discharge to be sufficiently discharged with a simple circuit configuration. This electrostatic discharge protection circuit includes a trigger circuit that has a first circuit and a second circuit that are connected in parallel between a first line and a second line, and a discharge circuit that is connected between the first line and the second line and has a transistor whose gate is directly or indirectly connected to a predetermined connection node of the trigger circuit, and that is turned on by a change in the gate potential.
The first circuit includes a first impedance element and a capacitor element that are connected in series between the first line and the second line, and a first transistor of a first conductivity type that is connected to the first impedance element in series and connected to the capacitor element in parallel. The second circuit includes a second transistor of a second conductivity type and a second impedance element that are connected in series between the first line and the second line. The gate of the second transistor is connected to a first node between the first impedance element and the capacitor element, the gate of the first transistor is connected to a second node between the second transistor and the second impedance element, and the predetermined connection node is the first node or the second node.
In this electrostatic discharge protection circuit, once the second transistor enters the on state due to an electrostatic discharge, the second transistor continues to hold the on state while the potential of the first line is higher than the potential of the second line, regardless of the CR time constant, and the charge applied to the first line due to the electrostatic discharge is released to the second line by the discharge circuit. However, if the electrostatic discharge protection circuit mistakenly starts to operate when the power supply voltage rises at the time of power activation, there is a risk of current continuing to flow as is to the discharge circuit.
JP A-2009-182119 (paragraphs 0003 to 0010, FIG. 9) and JP A-2014-132717 (paragraphs 0017 and 0018, FIG. 1) are examples of related art.